The invention relates to a process and a measurement device for heavy current testing of semiconductor components (hereinafter called chips). The chips to be tested can be present on wafers of semiconductor material (hereinafter called semiconductor wafers). The chips to be tested can also be individual chips cut from the semiconductor wafers.
For electrical testing of semiconductor components, especially power semiconductors, such as bipolar power transistors, MOS-FETS, power diodes and IGBTs, they are tested for heavy current suitability by applying a high measurement current (typically in the range from roughly 2 A to 200 A).
In doing so the chips which have not yet been installed in their housings and which are located next to one another (not yet separated) on the semiconductor wafer make electrical contact with the contact surfaces of the front of the chip via test contacts.
Contact-making takes place typically via a so-called needle card or probe card which consists of an arrangement of extremely fine probes which is geometrically matched to the chip which is to be tested. The needle card is connected to the test system which has current and voltage sources and different electrical measurement instruments for electrical testing of the chip.
Especially when testing heavy current components, but also for other semiconductor components, such as microprocessors, overloading of the individual probes and/or contact points between the probe and tested chip can occur due to overly high test currents. These current peaks subsequently lead to damage to the probes and/or the chip which is to be tested due to the high temperatures which occur in the process.
These overcurrents (current spikes) can have various causes; examples include the following:    1. Asymmetrical current distribution for probes connected in parallel: When currents are being measured which are higher than the current carrying capacity of individual probes, the test current is routed over two or more probes which are connected in parallel. In the ideal case the test current is divided uniformly among the probes. But in practice, for example due to the poorly conducting dirt (oxidation) on the contact points, differences occur in the contact resistances of the individual probes connected in parallel, which then leads to unequal current distribution between the probes and to overloading of individual probes.    2. If a chip is tested which for example has a defect which leads to a short circuit of the current source, the maximally flowing test current is determined by the current limitation of the source. Current limitations of the sources which are set too high or which react too slowly can lead to overloading of the probes.
For a long time the problem was solved by defective probes or even complete probe cards being replaced.
Another approach to prevention of overcurrents with probes connected in parallel is the use of resistors connected in series to the individual probes for current balancing. But to be effective they should be much larger than the variation of the contact resistances of the individual probes. But this increases the total resistance of the measurement path. This is especially undesirable in heavy current measurements.